The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
Each cell of a flash memory includes a gate structure in which a gate insulation film, a floating gate, an intermediate insulation film, and a control gate are laminated in this order. Hereinafter, a conventional method of manufacturing the flash memory will be discussed with reference to FIGS. 1A through 1D.
As shown in FIG. 1A, an element isolation film 21 is formed over a surface part of a substrate 20 including silicon and a plurality of activation regions provided in a lateral direction in FIG. 1A are determined. A first gate insulation film 23 is formed over a surface of the activation region. A floating gate 25a is formed over the first gate insulation film 23. In FIGS. 1A to 1D, current is caused to flow in a direction perpendicular to a plane of a sheet on which FIGS. 1A to 1D are illustrated. A source and a drain are provided on a near side and on a far side of the plane of the sheet, respectively. An intermediate insulation film 33 is formed over a surface of the floating gate 25a. 
A conductive pattern 35a including polycrystalline silicon extending in a lateral direction in FIGS. 1A to 1D is formed such that the conductive pattern 35a passes above the floating gate 25a and intersects with the activation region. The conductive pattern 35a fills between the mutually adjacent floating gates 25a and a top surface of the conductive pattern 35a is substantially flat. While, a step is formed at a part corresponding to an outer end of the outermost floating gate 25a over the top surface of the conductive pattern 35a. 
As shown in FIG. 1B, an insulation film 38 including silicon nitride is formed all over a surface of the substrate 20. As shown in FIG. 1C, anisotropic etching is carried out over the insulation film 38, thereby remaining a sidewall spacer 38a over a side surface of the conductive pattern 35a. At this stage, a unexpected residue 38b of the insulation film 38 may remain at the step over the top surface of the conductive pattern 35a. 
After forming the sidewall spacer 38a, a dopant is implanted into the source, the drain, and the conductive pattern 35a. 
As shown in FIG. 1D, a metal silicide film 43 is formed over the exposed surface of the conductive pattern 35a. The metal silicide film 43 is not formed over the area where the residue 38b still remains. A laminated structure including the conductive pattern 35a and the metal silicide film 43 forms a word line WL. The word line WL also serves as a control gate of each Field Effect Transistor (FET). An interlayer insulation film 50 is formed all over a surface of the substrate 20. A conductive plug 51 coupled to an end of the word line WL is formed through the interlayer insulation film 50.
The metal silicide film 43 is not formed over the area where the residue 38b still remains. In addition, the residue 38b blocks the dopant from being implanted into the conductive pattern 35a. This causes an increase in resistance of the word line WL. The increase in resistance of the word line WL leads to delay in writing data to a cell.